The present invention generally relates to solid-state memory devices. Particularly, the present invention relates to a structure for sensing and writing cells in an array of memory cells. More particularly, the present invention relates to an array of memory cells organized in bitlines and wordlines and a method for partial write and restore.
From U.S. Pat. No. 6,134,165 by John R. Spence, assigned to Conexant Systems, Inc., Newport Beach, Calif., US, filed Dec. 20, 1999, issued Oct. 17, 2000, “High speed sensing of dual port static RAM cell” a RAM array is known, comprising a RAM cell addressable by an access transistor connected to a bit line, a bit line precharge circuit for precharging said bit line to approximately one volt, a reference precharge circuit for producing a reference precharge signal, a sense amp having first and second sense amp inputs, wherein said first sense amp input is connected to said reference precharge signal and said second sense amp input is connected to said bit line, said sense amp detecting a value stored in said RAM cell when said RAM cell is addressed by said access transistor.
U.S. Pat. No. 6,195,280 by George McNeil Lattimore et al., assigned to IBM Corp., Armonk, N.Y., US, filed Mar. 9, 2000, issued Feb. 27, 2001, “Memory system having a unidirectional bus and method for communicating therewith” shows a memory and a method for communicating therewith are implemented having a unidirectional write bus for writing to memory cells within a plurality of memory cell groups. Local bitlines associated with each of the memory cell groups communicate write data to the associated memory cell. Global bitlines coupled to all of the memory cells are decoupled from the local bitlines during a write operation. Following a write operation the local bitlines are restored by a precharge operation during which the global and local bitlines are also decoupled.